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target/linx: execute PTO ISA v0.2 Tile profiles - #39

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LinxISA:masterfrom
jiale-wangOwO:feature/v057-pto-tile-execution
Jul 27, 2026
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target/linx: execute PTO ISA v0.2 Tile profiles#39
zhoubot merged 30 commits into
LinxISA:masterfrom
jiale-wangOwO:feature/v057-pto-tile-execution

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@jiale-wangOwO jiale-wangOwO commented Jul 24, 2026 •
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Summary

  • execute the PTO ISA v0.2 Tile target set on the LinxISA v0.57 encoding profile
  • retain PTO ISA v0.1 behavior for operations unchanged by the v0.2 update
  • add persistent Tile shape metadata, packed compare/select, signed narrow and FP16/BF16 arithmetic, reductions, expand/layout/partial operations, dequantization, TGEMV variants, TMATMUL_BIAS, interleave/de-interleave, and partial arg selection
  • freeze Tile source/output bindings before execution and publish queue-visible outputs only after successful completion
  • reject unsupported selectors and profiles before destination mutation instead of falling through to approximate or write-zero behavior
  • document the executable subset and fail-closed boundaries in docs/linxisa/pto-tile-support.md

This is the QEMU implementation subtask for LinxISA/SuperScalarModel#31. It does not close the tracking issue because gfrun, gfsim, and cross-model comparison work remains.

Version scope

  • previous semantic baseline: PTO ISA v0.1
  • current semantic target: PTO ISA v0.2
  • encoding profile: LinxISA v0.57

The 111-operation count is the complete current target set, not the number of operations newly introduced in PTO ISA v0.2. Earlier commit subjects that mention v0.57 refer to the LinxISA encoding profile; the existing PR history is preserved to avoid a force-push.

Coverage

  • TMA: 6/6 operations have execution paths
  • CUBE: 5/8 (TMATMUL, TMATMUL_BIAS, TMATMUL_ACC, TGEMV, TGEMV_ACC)
  • TEPL: 86/97 selectors have explicit execution paths
  • total: 97/111 operations
  • remaining fail-closed: 14

The count denotes at least one defined QEMU execution profile, not complete dtype, layout, shape, rounding, exception, or target-profile coverage. TQUANT, MX profiles, unresolved implicit-destination or variable-operand forms, and Pipe/control operations remain rejected until their contracts are closed.

Validation

  • ninja -C build qemu-system-linx64 PASS
  • dependent LinxISA AVS: python3 avs/qemu/run_tests.py --suite tile --timeout 40 PASS
  • call/ret contract PASS
  • QEMU opcode metadata sync PASS
  • ISA/QEMU L1 coverage report generation PASS
  • repository layout policy PASS
  • git diff --check PASS

The full LinxISA --all run has an existing unrelated liveness blocker at DeepSeek test 0x00001702; this PR does not report the focused Tile PASS as a full-suite PASS.

Dependent PR

Exact-value AVS coverage and the support matrix are maintained in LinxISA/linx-isa#159.

@jiale-wangOwO
target/linx: execute v0.57 TCMP packed predicates
10bce7a 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: fail closed on unsupported TEPL selectors
6d74c1f 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: honor signed narrow TEPL lanes
b15119a 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute FP16 and BF16 TEPL arithmetic
3bd6c2a 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: persist v0.57 tile shape metadata
e6d6d79 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TNEG
0741aeb 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TREM and TREMS
942a193 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TCMPS
f855d45 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TSEL and TSELS
344bb8a 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 product and arg reductions
61c2997 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 row and column expand variants
d97abd7 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TFILLPAD
d85773b 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 partial binary operations
3467c22 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 reshape concat and gatherb
ac80a14 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TCI and TTRI
17e76ea 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TEXTRACT
b5bab91 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TDEQUANT
dce81e4 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
target/linx: execute v0.57 TGEMV variants
ba5db86 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
@jiale-wangOwO
docs: record v0.57 PTO Tile execution status
6f326ae 
Signed-off-by: jialewang-316server <jialewangxox@gmail.com>
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@jiale-wangOwO jiale-wangOwO mentioned this pull request Jul 24, 2026
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@jiale-wangOwO jiale-wangOwO changed the title target/linx: execute the v0.57 PTO Tile subset target/linx: execute PTO ISA v0.2 Tile profiles Jul 26, 2026
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[HIGH] Blocking correctness issue in target/linx/helper.c:12381-12408, 12091-12160, 12582-12682, and 13033-13047: the TEPL selector whitelist is not paired with an operation-by-dtype/profile gate. TEXP, TLOG, TSQRT, TRSQRT, and TRECIP are admitted for FP16/BF16 because their element widths pass the global guard, but linx_tile_tepl_unary_word implements them only for FP32; the non-FP32 default returns zero, which is then written and published instead of raising LINX_EXCP_ILLEGAL_INST. FP8 basic arithmetic similarly falls through generic integer math. This contradicts the PR claim that unsupported profiles reject before destination mutation. Add explicit per-selector dtype/profile validation before the destination memset/execution and representative AVS coverage for rejected tuples without queue mutation. No CI checks are reported on this head, so the claimed local gates do not cover this missing semantic guard.

@jiale-wangOwO

jiale-wangOwO commented Jul 27, 2026

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Addressed the blocking TEPL profile review in commit 983afe0b42.

Changes:

  • added an explicit selector-by-dtype/profile gate covering all 86 executable TEPL selectors;
  • run the gate at linx_tile_append_iot() entry, before descriptor merge, source pinning, output reservation, destination memset, or queue publication;
  • retained the execution-time gate as defense in depth;
  • FP16/BF16 TEXP/TLOG/TSQRT/TRSQRT/TRECIP are rejected (current QEMU profile is FP32-only);
  • FP8/FPL8 arithmetic is rejected instead of falling through integer math;
  • documented the profile limits and pre-mutation rejection contract.

AVS evidence is in LinxISA/linx-isa#159:

  • 0x000A0029: FP16 TEXP raises illegal instruction, resumes, stores t#1, and verifies all 1024 lanes still match the original source;
  • 0x000A002A: same queue-nonmutation oracle for BF16 TLOG.

Local gates:

  • ninja -C build qemu-system-linx64: PASS
  • python3 -m unittest avs.qemu.test_run_tests: 17 PASS
  • python3 tools/isa/check_pto_v057_manifest.py --root .: PASS
  • focused verbose Tile suite with QEMU commit 983afe0b42: PASS, including both negative TEPL cases and all enabled TMA descriptor/layout/padding cases.

No CI checks are currently reported by GitHub on this head.

RuoyuZhou
Prevent TCVT from publishing misencoded narrow floats
ce26997 
The selector table closed destination-profile fallthrough, but TCVT also depends on the queued source dtype. Validate that tuple before pinning or reserving output and use QEMU softfloat for FP16/BF16 encoding boundaries.

Constraint: B.IOT rejection must precede source pinning and output reservation
Rejected: Disable FP16/BF16 TCVT entirely | current PTO workloads depend on those conversions
Confidence: high
Scope-risk: narrow
Directive: Keep TCVT source legality ahead of queue mutation and extend exact-value AVS with every new dtype tuple
Tested: linx64-softmmu build; focused Tile AVS including 0xA0016, 0xA0029, 0xA002A; strict opcode/meta audit; call/ret audit
Not-tested: full AVS beyond the known DeepSeek 0x1702 liveness blocker; live migration restore across v14/v15
Signed-off-by: RuoyuZhou <ruoyu.zhou@hisilicon.com>
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zhoubot approved these changes Jul 27, 2026
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Re-reviewed after the selector/dtype and TCVT repairs. Unsupported TEPL profiles now fail before queue/output mutation; TCVT validates the queued source dtype and uses QEMU softfloat for FP16/BF16. Verified linx64-softmmu build, focused Tile AVS (including negative IDs 0xA0029/0xA002A and exact TCVT ID 0xA0016), descriptor IDs 0xA000E-0xA0011, strict opcode/meta sync, and call/ret audit. Full AVS still reaches the known unrelated DeepSeek 0x1702 liveness blocker; strict L1 coverage remains an unchanged repository baseline gap.

@zhoubot
zhoubot merged commit 50e3e9a into LinxISA:master Jul 27, 2026
@jiale-wangOwO
jiale-wangOwO deleted the feature/v057-pto-tile-execution branch July 27, 2026 03:43
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